Process for forming a high density metallurgy system on a substrate and structure thereof

ABSTRACT

A process for forming a high density solder pad and fan-out metallurgy system in a ceramic substrate wherein a pattern of indented lines is formed in the surface of a green ceramic substrate, the lines filled with a conductive metal paste, a layer of dielectric green ceramic material deposited over at least a portion of the area of the pattern of indented lines, and sintering the resultant substrate.

This application is a division of Ser. No. 612,296 filed on May 21, 1984now U.S. Pat. No. 4,521,449.

TECHNICAL FIELD

This invention relates to forming metallurgy interconnection systems fordielectric substrates for semiconductor packages, and more particularlyfor the forming of a high density fan out pattern in a multi-layerceramic substrate.

Future semiconductor packages will be required to mount many highlyintegrated semiconductor devices, each with hundreds of circuits, on asingle substrate, and interconnect these devices into an operativesystem. This will require that the area of the package substrate besignificantly increased, as compared to present single and multipledevice package substrates now in common usage, the wiring densityincreased, and that many closely spaced bonding terminals forconnections to the semiconductor devices be provided. A structure thatcan potentially meet future high density package requirements is amulti-layer ceramic substrate. This structure is described in detail inU.S. Pat. No. 4,245,273. In this substrate the metallurgy is buriedwithin the substrate, making possible a very complex and intricatewiring interconnection. The basic process consists of forming a ceramicslurry of particulate ceramic material, a resin binder, and a solventfor the binder, doctor blading the slurry and drying to produce ceramicgreen sheets, punching holes in and screening conductive lines on thegreen sheets, laminating the sheets, and sintering.

Integrated circuit devices are becoming increasingly more dense andlarger, thereby necessitating more terminals that are increasingly moredensely spaced. In conventional multilayer ceramic substrates, usingsolder bonding techniques, the top sheet has a punched via configurationmatching the terminal configuration of the semiconductor device. The fanout of metallurgy lines is done in the several underlying layers.However, when the via holes are closely spaced, cracks may developbetween the vias during sintering due to the differential coefficient ofexpansion rates of the conductive material in the vias and the ceramicmaterial of the substrate. This presents a yield loss, or if no initialshort occurs, it presents a future potential problem. In addition, thelarge number of closely spaced terminals require increasingly largenumbers of underlying layers to provide the metallurgy line fan outfunction, which adds a significant cost factor to the substrate.

It is known to provide a surface metallurgy fan out pattern, completewith terminals on the top surface of the substrate, as suggested by U.S.Pat. No. 3,968,193. This surface metallurgy system consisting of one ormore layers may be provided by screening through a mask or with the useof photolithographic techniques applied after the substrate has beensintered. However, during sintering the substrates may undergo ashrinkage of about 17%. This shrinkage can be accommodated by designingthe unsintered substrates larger by the amount of the shrinkage. Theshrinkage is not always uniform throughout the area of the substrate.Certain areas may shrink more or less resulting in a distorted patternof vias on the surface. It may not be possible to align a screening maskor a mask exposing a resist to the pattern vias that must be connectedto establish contact with the internal metallurgy of the substrate. Theproblem is further enhanced as the vias become smaller and the sheetbecomes larger.

DISCLOSURE OF INVENTION

An object of this invention is to provide a process for forming asemiconductor package substrate having a conductive surface fan-outpattern interconnected to an internal metallurgy pattern.

Another object is to provide a substrate having an I/O metallurgypattern comprised of a conductive surface line pattern interconnected incombination with an internal metallurgy system.

Yet another object is to provide a process for forming a closely spacedterminal pattern for connecting to a semiconductor device and a fan outmetallurgy pattern on a substrate that does not require increasinglyclosely spaced vias in the top sheet, and provides a positive anddependable mode of contacting the underlying internal metallurgy with asurface metallurgy pattern.

In accordance with the aforementioned objects, the process of theinvention for forming a high density interconnection pattern andmetallurgy system for electrically connecting an integrated circuitsemiconductor device to a support substrate that embodies, providing anunsintered, green ceramic substrate with an internal metallurgy systemincluding a matrix of vias on the top surface filled with conductivemetal paste, forming indented areas in the top surface of the greenceramic sheet that are interspersed between the aforementioned vias, andindented lines that are joined to the indented areas that radiategenerally outwardly forming a fan out configuration, filling theindented areas and lines with a conductive metal paste, screening adielectric layer of ceramic material on the top surface of the substratethat covers the indented lines but leaves the vias and indented areasexposed, and sintering the substrate.

The high density, multiple interconnection pad and fan out metallurgyfor a multilayer ceramic module of the invention has a multilayerceramic substrate with an internal metallurgy system, a plurality ofvias arranged in a spaced matrix and an outer ring of vias surroundingthe matrix in the top surface of the substrate, a plurality of smallindented areas arranged in a matrix arranged within and with alternatingvias in the spaces between the matrix of vias, the matrix of areas, andthe matrix of indented areas collectively defining an interconnectionterminal configuration, a plurality of indented lines in the surface ofthe substrate, each of the indented lines terminating at one end at anindented area of the matrix, and at the opposite end to one of the viasin the outer ring of vias, conductive metal materials disposed in theindented lines, and in the indented areas forming the surface metallurgyfan out pattern, a dielectric layer of material provided with openingsover each of the vias in the matrix of vias, and each of the metalfilled indented areas in the matrix of indented areas, and a pluralityof terminal pads, each pad located over a via of the matrix of via holesand over an indented area of the matrix of indented areas.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating the various steps of the method ofthis invention,

FIG. 2 is a top surface view in greatly enlarged scale depicting aportion of a solder pad configuration and surface fan out metallurgysystem of the invention.

FIG. 3 is a sectional view taken on line 3--3 of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings, there is illustrated in FIG. 1 a flowchart that depicts the novel combination of method steps of theinvention for the fabrication of a high density metallurgy system in amulti-layer ceramic substrate. Block 10 directs that an unsinteredceramic substrate be provided. The basic structure of the ceramicsubstrate, preferably a multi-layer ceramic substrate is conventionalBlock 12 provides additional pads and conductor lines in the surface ofthe top layer in addition to the normally spaced punched vias. A sectionof the top surface indicating a preferred specific embodiment isindicated in FIG. 2 in substrate 20. The total terminal pad connectionfootprint for connecting to a semiconductor device consists of thecombination of circular vias 22 arranged in a matrix of rows andcolumns, and a second matrix of indented areas 24 interspersed betweenthe matrix of vias. As more clearly indicated in FIG. 3, a fan outstructure for vias 22 terminate in a series of vias 26 arranged in oneor more rows around the border of the pad terminal matrix configuration.As shown in FIG. 3, the via 22 extends downwardly through ceramic layers28 and 30 where it is joined to a metallurgy stripe 32 that is connectedto via 26, again terminating at the surface of the substrate in pad 38.The fan out arrangement in the internal layers of the substrate 20 canextend through more or fewer layers and can extend both in the X and theY directions normally on different layers. As is well known, thecombination of via 26, severable stripe 36 and pad 38 comprise what iscommonly known as an engineering change pad. In use, the line portion 36can be severed and appropriate connections made from pad 38 to otherappropriate terminals to correct internal metallurgy system for defectsor to make wiring changes. An important aspect of the unsinteredsubstrate 20 is that the density of vias 22 is less dense than the padsof the I/O connections to the device since intermediate connections aremade to pads 24. The surface metallurgy structure of the inventionconsists of surface fan out metallurgy including pads 24, surface lines40 joined to pads 24 and to pads 42. As indicated in FIG. 3, vias 44lead downwardly into substrate 20 and are interconnected to the internalmetallurgy of the substrate. Engineering changes can also be made to thesurface metallurgy pattern by severing the stripe 40 and joining thepads 42 by wires that are bonded to pad 42.

In order to form the surface metallurgy system on substrate 20 a patternof indented surface areas 24 and indented lines 40 is made in thesurface of the substrate. The indentations are possible since thesubstrate is in its green state and is thus deformable. In addition, theindentations can be aligned to other surface features on the substratesuch as vias 42 and proper spacing maintained between vias 22 since thesubstrate is in its green state and has not yet been deformed by thenormal sintering operation. The indented surface features can be formedby making a die containing embossed areas and lines in the desired shapeof the indented features in the reverse pattern desired on thesubstrate. The die can be produced by any conventional metal moldingprocess such as photolithographic techniques to form a pattern over theareas to be raised, followed by a metal removing operation such as metaletching, sputter etching, or electrolytic metal removal techniques.After the die with the embossed lines formed in the reverse image of thepattern, is positioned on the substrate, it is forced inwardly by asuitable pressure and temperature-applying technique such as alamination press thereby forming indented areas 24, 42 and indentedlines 40. The indentations can also be formed by eroding away thesurface of the substrate, as by e-beam, laser, or analogous techniques.

The shape, width and depth of the lines can be any dimensions consistentwith the associated dimensions of the substrate and sheets. Preferably,the depth of the lines and areas will be in the range of 0.3 to 2 mils.The width of the indented lines will be in the range of 0.5 to 2 mils,more preferably from 1.0 to 2.0 mils. Preferably the ratio of the widthof the lines to the depth will be of the order of 2:1 to 1:1.

Block 14 indicates that the next step in the process of the invention isfilling the indented pattern, i.e. the indented areas 24 and indentedlines 40 with a conductive paste. If the substrate is formed of amaterial, such as alumina that requires a high sintering temperature,the conductive paste must be of a refractory metal. The paste is wellknown consisting basically of a particulate refractory metal i.e. Mo, Wor Ta, combined with a resin and a solvent for the resin along withplasticizers if desired. If, however the material of the substrate is aglass-ceramic material having a sintering temperature that is not ashigh as alumina, other suitable metals with higher conductivities, suchas copper can be used. In any event, the conductive paste applied to theindented pattern must be capable of withstanding the subsequentsintering operation. The paste can be applied by any suitable technique,as for example, wiping the surface of the substrate with a suitableapparatus which selectively deposits the paste in the indentations. Abetter technique for applying the paste in the indentations is to firstapply a thin plastic film over the surface of the substrate, andsubsequently form indentations. The plastic film facilitates thedeposition of the conductive material in the indentations. A techniquefor applying conductive paste into indentations in a substrate isdescribed in greater detail in IBM TDB April 1974 P. 3561. In thisprocess the Mylar sheet, used as a coating base for doctor blading theceramic slurry, is initially coated with polyvinyl alcohol. On peelingthe cast green sheet from the casting base sheet, the polyvinyl alcoholcoating strongly adheres to the green ceramic sheet forming a thinsmooth uniform surface film. Indentations of the desired patterns arethen pressed into the coated green ceramic sheet. The film will allowindentations to be formed. The conductive paste is squeezed into theindentations and the solvent allowed to evaporate. The film is burnedoff during sintering. Alternately, the surface film can be applied tothe green sheet after it has been cast, either as a coating or a precastsheet. Instead of polyvinylalcohol, polyamide may be used.

Block 16 indicates that the next step in the process of the inventioninvolves selectively applying a dielectric layer 50 over the area of theterminal pad configuration. The dielectric layer 50 should not extendover the rows of engineering pads 42, 36 and 38. The dielectric layer isapplied over the I/O terminal area in order to prevent solder bridgingbetween the very closely spaced via I/O pads and the lines when thedevice is solder bonded to the pad configurations. Preferably the deviceis joined to the pad configurations utilizing solder joining asdescribed in detail in U.S. Pat. Nos. 3,495,113 and 3,429,040. Mostpreferably the dielectric layer 50 is formed of a material that willwithstand the sintering operation. A preferred material is a ceramicslurry similar to the ceramic slurry used to fabricate the green ceramicsheets of the substrate. It is understood that various combinations ofsolvent and organic thickening (thixotroping) agents may be used forconvenience in screening. To avoid weakening the unfired metal lines atthe edge of the screened ceramic area, the slurry is preferablyconstituted so that it does not weep solvent after screening. Theceramic slurry can be applied over the pad area through a suitablescreening mask. The mask must provide block out areas to avoid applyingthe ceramic materials over the via 22 and indented area pads 24. Thethickness of the dielectric layer is most preferably in the range of 0.1to 1.0 mils. After the dielectric layer has been applied over the padarea, the substrate is sintered in the conventional manner as indicatedby block 18. During the sintering operation, the substrate will normallyundergo a shrinkage of approximately 17% depending on the ceramic, thesintering conditions, etc. Further, the substrates may be somewhatdistorted during the sintering operation, but the distortion, if anyoccurs, will not be so serious as to distort the location of theindividual pad areas used to join the substrate to a semiconductordevice. The fine alignment steps have all been completed prior tosintering.

Following the sintering operation, the metallurgy areas including vias22, pads 24, the engineering change pads and vias 42 and the indentedpatterns not covered by the dielectric layer can be coated with asuitable metal to make the pads solder wettable, and the associatedengineering change pads coated with a metal capable of permitting wiresto be joined by thermal compression bonding or other techniques.Conventional techniques are utilized to form this metallurgy on thesurface of the substrate.

While the invention has been illustrated and described with reference topreferred embodiments thereof, it is to be understood that the inventionis not limited to the precise construction herein disclosed and theright is reserved to all changes and modifications coming within thescope of the invention as defined in the appended claims.

We claim:
 1. A high density multiple interconnection solder pad andfan-out metalurgy system for a multi-layer ceramic module comprising,amulti-layer ceramic substrate having an internal metallurgy system, aplurality of vias arranged in a closely spaced matrix, and an outer ringof vias surrounding said matrix in the top surface of said substrate, aplurality of small indented areas arranged in a closely spaced matrixarranged within and with attending areas in the spaces between saidmatrix of vias, said matrix of vias and matrix of indented areascollectively defining an interconnection pad configuration, a pluralityof indented lines in said surface of said substrate, each of saidindented lines terminating at one end at an indented area of saidmatrix, and at the opposite end at one of said vias in said outer ringof vias, conductive metal material disposed in said indented lines andin said indented areas forming a surface metallurgy fan-out pattern, adielectric layer of material provided with openings over each of saidvias in said matrix of vias, and each of said metal filled indentedareas in said matrix of indented areas, and a plurality of solder pads,each pad located over a via of said matrix of vias, and over an indentedarea of said matrix of indented areas.